Crystal Oscillator Load Capacitance Calculator (CL & Caps)

Crystal Oscillator Load Capacitance Calculator

Match the two external capacitors on a Pierce oscillator using CL = (C1 x C2)/(C1 + C2) + Cstray. Find the load capacitance your crystal actually sees, size the symmetric caps C1 = C2 to hit its specified CL, and estimate the frequency pulling error in ppm and Hz from the shunt and motional capacitance.

Choose a Mode

🎯Real Oscillator Presets

📝Crystal & Circuit Inputs

Datasheet target load, often 8 to 20 pF.

Trace, pad and pin capacitance per leg, 2 to 5 pF.

External cap from XTAL1 pin to ground.

External cap from XTAL2 pin to ground.

Marked frequency; used for the Hz error output.

Static parallel capacitance of the crystal.

Series-arm capacitance in femtofarads; drives pulling.

Controls rounding on the result cards.

Actual CL seen by crystal 0 pF series C1,C2 plus Cstray
Recommended C1 = C2 0 pF to hit the specified CL
Capacitance error 0 pF actual CL minus spec CL
Estimated frequency error 0 ppm pulling from CL mismatch

🔢Formula Snapshot

CLC1C2/(C1+C2)+Cs
C2(CL − Cs)
ΔCLactual − spec
ppmCm / 2(C0+CL)

📋Typical Load CL by Crystal Type

Crystal / ApplicationFrequencyTypical CLNotes
Watch / RTC tuning fork32.768 kHz6 to 12.5 pFLow drive, high Q
Ultra low CL AT-cut8 to 40 MHz8 pFSmall pin caps
Low CL general4 to 50 MHz10 pFCommon SMD part
USB / MCU standard8 to 25 MHz12.5 pFVery widespread
Legacy through-hole1 to 20 MHz16 pFOlder HC-49 cans
Classic microcontroller4 to 24 MHz18 pFAVR / PIC default
High CL / robust1 to 30 MHz20 pFTolerant of stray
Fundamental HF can20 to 50 MHz20 to 30 pFCheck drive level

📊Symmetric Cap Lookup (C1 = C2)

Spec CLCstray 2 pFCstray 3 pFCstray 5 pFFormula
8 pF12 pF10 pF6 pF2(CL − Cs)
10 pF16 pF14 pF10 pF2(CL − Cs)
12.5 pF21 pF19 pF15 pF2(CL − Cs)
16 pF28 pF26 pF22 pF2(CL − Cs)
18 pF32 pF30 pF26 pF2(CL − Cs)
20 pF36 pF34 pF30 pF2(CL − Cs)
22 pF40 pF38 pF34 pF2(CL − Cs)

📏Stray Capacitance Budget Guidance

ContributorTypical ValueRangeLayout Note
MCU oscillator pin2 pF1 to 5 pFRead pin CL in datasheet
Short PCB trace1 pF0.5 to 2 pFKeep tracks under 10 mm
Pad and via0.5 pF0.3 to 1 pFMinimize copper area
Ground guard ring0.5 pF0.2 to 1 pFAdds but cuts noise
Total typical Cstray3 pF2 to 5 pFUse per single leg
Loose long-trace layout5 to 7 pFup to 10 pFAvoid; degrades CL match

🗃Crystal Parameter Comparison Grid

Crystal TypeFrequencySpec CLMax ESRC0 ShuntCm MotionalDrive LevelTolerance
Watch tuning fork32.768 kHz12.5 pF50 kΩ1.35 pF3 fF1 µW±20 ppm
RTC low CL32.768 kHz6 pF70 kΩ1.1 pF2.5 fF0.5 µW±20 ppm
Low CL SMD12 MHz10 pF80 Ω2.5 pF12 fF100 µW±30 ppm
USB / MCU16 MHz12.5 pF50 Ω3 pF10 fF100 µW±30 ppm
Classic MCU8 MHz18 pF60 Ω3.5 pF14 fF200 µW±50 ppm
Ethernet PHY25 MHz18 pF40 Ω4 pF9 fF200 µW±50 ppm
CAN node20 MHz20 pF30 Ω4 pF8 fF300 µW±30 ppm
HF fundamental40 MHz20 pF30 Ω5 pF6 fF300 µW±50 ppm

Formula Breakdown

Series of two capsTwo grounded load caps sit in series across the crystal, so their combined value is (C1 x C2) / (C1 + C2). Equal 30 pF caps give 900 / 60 = 15 pF.
Actual CL = series + CstrayAdd the parasitic stray on the two pins and traces. With 15 pF series and 3 pF stray, the crystal actually sees CL = 15 + 3 = 18 pF.
Match caps C = 2(CL − Cstray)For symmetric C1 = C2, invert the series formula. To reach an 18 pF spec with 3 pF stray, C = 2 x (18 − 3) = 30 pF each.
Capacitance error ΔCLCompare what the crystal sees to its spec: ΔCL = CL_actual − CL_spec. A positive value means the caps are too large and the frequency runs low.
Pulling sensitivity SThe fractional frequency change per pF is S = Cm / (2 x (C0 + CL)²), from the parallel-resonance model. Larger Cm or smaller C0+CL means more pull.
Frequency error in ppmMultiply sensitivity by the mismatch: Δf/f ≈ − Cm x ΔCL / (2 x (C0 + CL_spec) x (C0 + CL_actual)), then scale by 1e6 for ppm.
Frequency error in HzConvert ppm to hertz with Δf = (ppm / 1e6) x f0. At 16 MHz, 10 ppm equals 160 Hz of offset from the marked value.

💡Load Capacitor Design Tips

Budget stray before choosing caps: A crystal specified for 18 pF with 3 pF of stray per leg needs only 30 pF caps, not 36 pF. Ignoring the 2 to 5 pF of pin and trace capacitance oversizes both caps and pulls the oscillator a few dozen ppm low, which is often enough to break tight USB or RTC timing.
Keep C1 equal to C2 and short: Symmetric caps give the Pierce loop clean, balanced drive; a 22 pF versus 33 pF split skews the phase and can raise startup ESR. Hold the tracks under about 10 mm and add a ground guard to keep stray near 3 pF so the modeled CL matches the real board.

Is it oscillating like an out-of-tune orchestra? Your microcontroller won’t lock. You’ve used the right part number. You can read the schematic and everything seems right. You’ve even taken special care to solder every joint. The system doesn’t enumerate or worse yet, it’s drifting out of time by several seconds per hour.

Don’t blame the chip. Rarely is this a bad chip. Nine times out of ten, it’s a capacitor problem: specifically, sizing your capacitors in relationship to stray capacitance on your pins and traces. This calculator will do the math for you, no more guessing why your oscillator are running at the wrong frequency.

Why Your Clock Is Wrong

The thing about a quartz crystal is that it’s not going to vibrate at one fixed frequency; rather, it behaves as a parallel shunt capacitor with a high-Q series resonant circuit with a motional arm. Only if it is loaded with a certain amount of capacitance across its terminals will it start to oscillate on its marked frequency. That capacitance is known as load capacitance or CL. If you apply the incorrect value there, it’ll run the oscillator, but pull it off spec. A couple of tens of parts per million may not sound significant, but it’s enough to blow up a real-time clock or fubar USB timing.

You need to stop and think about exactly what is connected. On each side of crystal are two grounded capacitors in a typical Pierce oscillator. As far as the crystal sees them, those two capacitors appear in series with each other. What does that mean? You know how if you have two capacitors in series then their series equivalent is the product divided by the sum? Well, not quite. There is always some stray capacitance involved: from the traces and pads and pins that electrically connect the crystal to the capacitors. And that stray capacitance are part of the series circuit that the crystal “sees.” The full expression the crystal experiences is the series combination of your two caps plus that stray value.

If there were 3pF of capacitance on each leg, and your two capacitors was both 30 pF, then together they’d be 15 pF in series. Add the stray and the crystal sees 18pF. This is perfect for a common spec on a microcontroller.

Capacitors are symmetric in most designs; C1 = C2. This provides a balanced drive of the oscillator loop and the cleanest start up behavior. If you make both caps C then math simplifies nicely, and it’s half that plus stray capacitance to the crystal. To find the right capacitor value for a spec CL, solve for the capacitor first. Take twice the difference from the spec CL and subtract the stray capacitance you expect on each side.

That’s where folks go awry. They forget to account for the stray capacitance and just double the spec. This results in a capacitor that is too large and pulls frequency down. For beginners: Stray capacitance is the term they forget, while experts obsess over it. This is mostly between 1 and 5 pF from the oscillator input pin of the chip itself; add in the ground guard ring around the crystal, as well as pads, vias, and copper traces connecting everything together, and you can expect to have roughly 3 pF per leg in a compact layout. This parasitic effect is added right into the load, so if you ignore it your design will slowly wander away.

The calculator shows how far you are off. In both hertz and parts-per-million, or ppm. By assuming motional and shunt capacitance numbers from the datasheet it provides a reasonable guess at that change, with something to stand behind. You don’t need to learn this to use the tool; just know that the ratio between motional capacitance and total load determines the device’s sensitivity. In particular, watch crystals at 32.768 kHz has extremely small motional capacitance, around 3 fF, which makes them very sensitive to their load. This explains the fussiness of an RTC layout in terms of component placement.

As you move up in frequency, the pull becomes gentler, but when you’re after narrow tolerances, every picofarad matters. From 16 MHz microcontrollers to 25 MHz Ethernet references, the preset buttons on the page cover what engineers encounter most frequentley. Select the closest preset to your design, tweak the stray capacitance to fit your board layout, then read the results. You’ll get the estimated frequency shift, the capacitance error, the recommended symmetric cap value for hitting spec, and even the actual load that will be seen by the crystal. It turns the abstract series-load formula into quick and reliable numbers you can trust.

But you know, one of the first things to get right is to get your caps right. And to do that is to get your clock right when you factor in what’s already there on the board before you add any other component from outside. Once you do that, you stop fighting the physics and work with them.

Small thing? Yes. But it matters.

Crystal Oscillator Load Capacitance Calculator (CL & Caps)